The present invention relates to nonvolatile semiconductor storage devices and, more particularly, to a nonvolatile semiconductor storage device of a type that a dummy cell array region is placed around a memory cell array region.
Generally, in a nonvolatile semiconductor storage device, a dummy cell array region is placed outside a memory cell array region. FIG. 2 is a schematic view of a common semiconductor storage device. A dummy cell array region 200 is placed so as to surround a memory cell array region 100.
It has become essential to place dummy cells (not shown) in the dummy cell array region 200 in order to uniformize the characteristics of the nonvolatile semiconductor storage device. This is due to the following reason. That is, whereas the configuration of the gate electrode that strongly affects the performance of memory cells (not shown) of the memory cell array region 100 is determined by exposure conditions and etching conditions, these conditions are strongly affected by peripheral patterns. If the dummy cell array region 200 is not provided, the gate electrodes of memory cells are indeed regularly arranged inside the memory cell array region 100 but this regularity would collapse in the outer periphery. On this account, there would arise differences in the configuration of gate electrodes in the outer periphery of the memory cell array region 100, which would cause variations in memory cell characteristics.
Thus, to avoid this, the dummy cell array region 200 is placed outside and around the memory cell array region 100 as shown in FIG. 2 so that a regular arrangement pattern of gate electrodes is given also in the outer periphery of the memory cell array region 100.
Therefore, dummy cells in the dummy cell array region 200 are formed so as to have a device configuration as well as a layout configuration closest possible to those of the original memory cells, while the dummy cells do not function as memory cells and are required to be electrically isolated from the memory cells so as not to affect the operation of the original memory cells.
FIG. 3 shows a circuit diagram of the memory cell array region 100 and the dummy cell array region 200 of a known ETOX (EPROM Thin Oxide) type nonvolatile semiconductor storage device. In the memory cell array region 100, each memory cell (field-effect transistor) MCELL has drain and source. In the memory cell MCELL, the drain is formed independently, and this drain is connected to a main bit line MBL while the source is connected to Vss (GND level). By desired word lines WL being selected, desired memory cells MCELL are selected, and currents flowing through the memory cells MCELL via main bit lines MBL0, MBL1, . . . are sensed, by which data is read. Meanwhile, in the dummy cells DCELL, although memory cells are formed as in the regular memory cells MCELL, the drain is floating, with current paths not present, having no effects on the memory cell array region 100. Thus, the dummy cell array region 200 is electrically isolated from the regular memory cell array region 100.
However, in recent years, there has been a demand for larger capacity and lower power consumption of flash memories, and attention is focused on flash memories of the virtual-grounding array configuration capable of high integration suitable for that demand.
This is exemplified by an ACT (Asymmetrical contactless transistor) flash memory announced in "A sensing scheme for an ACT flash memory," Proceedings of The Institute of Electronics, Information and Communication Engineers, ICD 97-21, p. 37, 1997.
This ACT flash memory employs FN (Fowler-Nordheim) tunneling phenomenon for programming and erasure, thus capable of lowering the power consumption.
The ACT flash memory is explained with reference to FIGS. 4 and 5A, 5B.
The ACT flash memory employs the FN tunneling phenomenon for programming and erasure as described above, and has a virtual-grounding array configuration in which one main bit line MBL is shared by two rows of memory cells MCELL.
As schematically shown in FIG. 4, one main bit line MBL is shared by both side memory cells MCELL, and a diffusion layer is used for sub-bit lines SBL so that the number of contacts 9 is reduced, making the array area significantly decreased. Thus, a higher integration is enabled.
Referring to FIG. 4, MBL0-MBLn+1 denote main bit lines, SBL0-SBLn+1 denote sub-bit lines formed by the diffusion layer, WL0-WL63 denote word lines, SG0 denotes a gate line for select transistors 4 for selecting this block, numeral 9 denotes contacts between the main bit lines MBL and the sub-bit lines SBL (different in hierarchy from the main bit lines MBL).
Next, a cross section of the ACT flash memory device is shown in FIGS. 5A and 5B.
This ACT flash memory device has, on a substrate 11, sub-bit lines SBL (diffusion layer), tunneling oxide 12, floating gates FG, an interlayer insulator 13 and control gates WL (continuing to word lines WL and shown by the same reference character as the word lines WL) in a layered structure. Then, the common sub-bit line SBL provided under end portions of the neighboring floating gates FG is differentiated in donor concentration between drain and source sides.
Next, programming and erasure onto the ACT flash memory by using the FN tunneling phenomenon are explained.
First, a programming operation is carried out, as shown in FIG. SA, by applying a negative voltage (-8 V) to the control gate WL of a desired memory cell MCELLm, applying a positive voltage (+5 V) to the drain side via the sub-bit line SBL, and bringing the source side into a floating state.
As a result, an FN tunneling phenomenon occurs to the drain side of the memory cell MCELLm, by which electrons are pulled out from the floating gate FG to the drain side. Then the threshold of the memory cell MCELLm lowers to about +1.5 V, thus resulting in a programmed state.
An erasing operation, on the other hand, is carried out, as shown in FIG. 5B, by applying a positive voltage (+10 V) to the control gate WL of a desired memory cell MCELLm, and applying a negative voltage (-8 V) to the substrate (p-type well) 11 and further by applying a negative voltage (-8 V) to the source and drain sides via the sub-bit line SBL. As a result, a FN tunneling phenomenon occurs to between a channel layer 14 and the floating gate FG, by which electrons are injected into the floating gate FG. Then the threshold of the memory cell MCELLm rises to about +4 V or more, thus resulting in an erased state.
A flash memory using the FN tunneling phenomenon for both programming and erasing operations as shown above is called FN-FN operational flash memory.
Also, a reading operation is carried out by applying +3 V to the control gate WL of a desired memory cell MCELL, applying +1 V to the drain and applying 0 V to the source via the sub-bit lines SBL. Then the current flowing through the memory cell MCELL is sensed by an unshown sensing circuit, by which data is read out.
Applied voltages to the memory cell MCELL involved in the above operations are listed in the following Table 1:
TABLE 1 Applied voltages of ACT flash memory: P-type Control gate Drain Source well Program -8 V 5 V Open 0 V Erase 10 V -8 V -8 V -8 V Read 3 V 1 V 0 V 0 V
The virtual-grounding array configuration including dummy cells of the ACT flash memory is shown in FIG. 6.
Referring to FIG. 6, a portion surrounded by one-dot chain line is a dummy cell array region 400, and the dummy cell array in this dummy cell array region 400 is made into the same configuration as the original memory cell arrays in a memory cell array region 300 as described above. However, this dummy cell array, unlike the regular memory cell array, has no function of setting the threshold high by injecting electrons into the floating gate of a dummy cell DCELL.
A reading operation with occurrence of problems in this configuration is explained with reference to FIG. 6.
For example, let us consider a case where a memory cell MCELL2 is read. First, for selection of a block "n" (hereinafter, referred to as BLOCKn), gate SGn of a select transistor 4 is turned ON (+3 V is applied to gate SGn), and then +3 V is applied to a desired word line WL (WL0N in this example) out of the word lines WL0n-WL31n. Meanwhile, 0 V is applied to word lines (WL1n-WL31n in this example) to which the gates of the non-select memory cells are connected, while 0 V is applied also to the substrate (p-type well).
Then, +1 V is applied to a main bit lines MBL2, which is connected to the drain of the memory cell MCELL2, and 0 V is applied to a main bit lines MBL3 connected to the source.
As a result of this, if the memory cell MCELL2 is in the programmed state (with threshold low), a current flows from the main bit line MBL2 via its sub-bit line SBL and memory cell MCELL2 to the main bit line MBL3. On the other hand, if the memory cell MCELL2 is in the erased state (with threshold high), no current flows from the main bit line MBL2 and its sub-bit line SBL via the memory cell MCELL2 to the main bit line MBL3.
This current is sensed by a sensing circuit connected to main bit line MBL2, which is not shown, and whether the memory cell MCELL2 is in the programmed state or the erased state is read as data ("1" or "0").
However, in the virtual-grounding array configuration, since a main bit line MBL (sub-bit line SBL) is shared by two neighboring memory cells MCELL as described before, reading of data from a memory cell MCELL is affected by the state of its neighboring memory cell MCELL.
For example, when reading a memory cell MCELL in the erased (high threshold) state, if its neighboring memory cells MCELL0 and MCELL1 are programmed (low-threshold) state, a current would flow to the main bit line MBL0 (with 0 V applied) via the memory cells MCELL0 and MCELL1 from the main bit line MBL2 (with 1 V applied) through its sub-bit line SBL.
In principle, a current would not flow in the reading of the memory cell MCELL2. However, because of this sneak current, the sensing circuit connected to the main bit line MBL2 may sense a current, which would bring about a programmed state and a misreading of the memory cell MCELL2.
To avoid this, a 1 V is applied also to a neighboring main bit line (MBL1 in this example) so that unnecessary sneak current does not occur regardless of the state of the memory cell MCELL1 or MCELL0. Thus, a desired level of the main bit line MBL2 is established.
Because of the virtual-grounding array configuration, the same thing would occur also to the dummy cell array region 400. That is, there has been a possibility that in the case of selecting and reading a memory cell MCELL located in outer peripheral portion, the dummy cells DCELL, which are originally intended to eliminate any variations in characteristics of the memory cells MCELL which are located in the outer periphery of the memory cell array region 300, causes a lowering reading margin and besides a misreading of the memory cell MCELL located in the outer peripheral portion due to an effect of a neighboring dummy cell DCELL (in this case, charging current or leak current to floating capacity of dummy cell DCELL) as described above. In addition, there has been no function of setting high the threshold of the dummy cells DCELL of the dummy cell array region 400.